1. Field of the Invention
This invention relates to a plasma display and a drive method for use on a plasma display, and more particularly to a plasma display and a drive method for use on a plasma display which are suitably used in improving the variations in brightness of display in a plasma display panel.
2. Description of the Related Art
The plasma display, including a plasma display panel (hereinafter, referred also to as “PDP”) as its major part, has many features, e.g. sliminess and relative easiness to make a large-screen display, wide viewing angle, high response speed and so on. Consequently, it is a recent practice to make use of it as a flat panel display, in a wall-mounted TV and a communal display.
The plasma displays are classified into a certain number of kinds depending upon the operation schemes thereof. The PDPs, manufactured presently on a commercial basis, adopts “Address Display Separate method (ADS)” in which completely separated are a scanning time period for writing display data to the cell and a sustaining time period for effecting display by an actual discharge. In the Address Display Separate method, after all the display data is written in the scanning time period, on-screen display is performed by applying a sustain pulse simultaneously to all the cells in the sustaining time period, thus simplifying the internal circuit to a comparative extent. Besides, drive margin is easy to secure because of no coexistence, on the panel, of a write discharge for writing display data to the cell and a sustain discharge for making a display at the same time. By virtue of those merits, the Address Display Separate method is adopted in the existing plasma displays.
The plasma display of this kind is conventionally constructed with a display panel (PDP) 1, a data driver 11, a scanning driver 12, a sustain driver 13, a charge recovering circuit 14, a power supply circuit 15, a signal processing circuit 21 and a control circuit 22, as shown in FIG. 1 for example. The PDP 1 has front and back substrates, not shown, arranged opposed to each other. On an opposed surface of the front substrate to the back substrate, scan electrodes 2 and sustain electrodes 3 are arranged parallel one with another with a spacing of a not-shown discharge gap. Scan pulses for write discharge are sequentially applied to the scan electrode 2. Meanwhile, the scan electrodes 2 and the sustain electrodes 3 constitute pairs of-surface-discharge electrodes, to which a sustain pulse is applied to cause a sustain discharge. On the opposed surface of the back substrate to the front substrate, a plurality of data electrodes 4 are provided in the form intersecting with the surface-discharge electrodes. A data pulse and erase-data pulse are applied to the data electrodes 4. Unit cells 5 are formed at the intersections of the surface-discharge electrode pairs and the data electrodes 4.
The data driver 11 is to apply a data pulse and erase-data pulse corresponding to display data z to the data electrode 4. The scanning driver 12 is to apply a scan pulse and erase pulse to the scan electrode 2. The sustain driver 13 is to apply a sustain pulse to the sustain electrode 3. The charge recovering circuit 14 is to restore the capacitance component charge of the PDP 1 and establish a potential on the scan electrode 2 and sustain electrode 3 of the PDP 1, under control of the control circuit 22.
The power supply circuit 15 is to supply a predetermined high-voltage power to the data driver 11, the scanning driver 12, the sustain driver 13 and the charge recovering circuit 14. The signal processing circuit 21 is configured by a not-shown A/D (analog/digital) conversion circuit, pixel conversion circuit, sub-field conversion circuit and so on. An analog video signal “in” is converted into a digital video signal by the AD conversion circuit, the number of pixels of the video signal is converted into the number of pixels corresponding to the PDP 1 by the pixel conversion circuit to thereby generate a video signal, and the video signal of from the pixel conversion circuit is converted into sub-field-based display data z by the sub-field conversion circuit and forwarded to the data driver 11. The control circuit 22 takes control of the operation timing of the data driver 11, the scanning driver 12, the sustain driver 13 and the charge recovering circuit 14, to thereby control the input of a voltage generated by the power supply circuit 15. Timing signals (horizontal synchronizing signal, vertical synchronizing signal) H, V are inputted to the signal processing circuit 21 and control circuit 22, to take a synchronism of the operation thereof with a screen displayed.
FIG. 2 is a structural view showing the major part of the PDP 1 in FIG. 1.
In the PDP 1, there are arranged a group of surface-discharge electrodes formed with scan electrodes 2 (Scani, i=1, 2, . . . , n) and sustain electrodes 3 (Susi, i=1, 2, . . . , n) that are in the number of n and are extending in a row direction H and arranged parallel one with another on an inner surface of a not-shown front substrate, and data electrodes 4 (Dj, j=1, 2, . . . , m) which are in the number of m and are arranged extending along a column direction V and orthogonally to the surface-discharge electrode group on an inner surface of a not-shown back substrate. Unit cells 5 are respectively formed at the intersections of the surface-discharge electrode group and the data electrodes 4. Thus, cells are arranged in a matrix form in the row direction H and the column direction V. For monochromatic display, one cell constitutes one pixel whereas, for color display, one pixel is constituted by three cells (emission cells for red R, green G and blue B).
FIG. 3 is a cross-sectional view of the unit cell 5 taken on line A-A in FIG. 2.
In the unit cell 5, a front substrate 11 and a back substrate 12 are oppositely arranged with a predetermined spacing, as shown in FIG. 3. The front substrate 11 is structured by a glass substrate or the like, on which front substrate 11 a scan electrode 2 and a sustain electrode 3 are arranged spaced with a discharge gap 13. Those scan electrode 2 and sustain electrode 3 constitute a surface-discharge electrode pair 6. Furthermore, a transparent dielectric layer 14 is formed over those electrodes, and a protection layer 15 is formed on the transparent dielectric layer 14. The protection layer 15 is structured of MgO or the like, thus protecting the transparent dielectric layer 14 from a discharge. Meanwhile, the back substrate 12 is structured by a glass substrate, on which back substrate 12 the data electrode 4 is provided orthogonally to the scan electrode 2 and sustain electrode 3. Furthermore, a white dielectric layer 16 is provided over the data electrode 4, on which white dielectric layer 16 a phosphor layer 17 is provided. Between the front substrate 11 and the back substrate 12, a curb-formed partition wall 18 is formed in a manner surrounding the cell. The partition wall 18 serves to secure a discharge space 19 and demarcate pixels. The discharge space 19 is sealed therein with a mixture gas of He, Ne, Xe or the like as a discharge gas.
FIG. 4 is a circuit diagram showing an electric configuration of the PDP 1 and charge recovering circuit 14 in FIG. 1.
The charge recovering circuit 14 is configured with a resonant circuit 30 and clamping circuits 40, 50, as shown in FIG. 4. The resonant circuit 30 is configured with an inductance 31, a diode 32, switches S1, S2, a diode 33 and an inductance 34. In the resonant circuit 30, the switches S1, S2 are controlled as to on/off state by the control circuit 22. When the inductance 31 or inductance 34 and the capacitance component of PDP 1 become a resonant state, the charge on the capacitance component of PDP 1 is restored by the inductance 31 or 34.
The clamping circuit 40 is configured with switches S3, S4 and diodes 41, 42. In the clamping circuit 40, the switches S3, S4 are controlled as to on/off state by the control circuit 22, to set the scan electrode 2 of PDP 1 at a voltage Vs or a ground level. The clamping circuit 50 is configured with switches S5, S6 and diodes 51, 52. In the clamping circuit 50, the switches S5, S6 are controlled as to on/off state by the control circuit 22, to set the sustain electrode 3 of PDP 1 at a voltage Vs or a ground level.
FIG. 5 is a circuit diagram showing another electric configuration of the charge recovering circuit 14 in FIG. 1.
The charge recovering circuit 14 is configured with resonant circuits 60, 70 and clamping circuits 80, 90, as shown in FIG. 5. The resonant circuit 60 is configured with an inductance 61, a diode 62, switches S1, S2, a diode 63, an inductance 64 and a capacitance 65. In the resonant circuit 60, the switches S1, S2 are controlled as to on/off state by the control circuit 22. When the inductance 61 or inductance 64, the capacitor 65 and the capacitance component of PDP 1 become a resonant state, the charge on the capacitance component of PDP 1 is restored by the capacitor 65.
The resonant circuit 70 is configured with an inductance 71, a diode 72, switches S3, S4, a diode 73, an inductance 74 and a capacitance 75. In the resonant circuit 70, the switches S3, S4 are controlled as to on/off state by the control circuit 22. When the inductance 71 or inductance 74, the capacitor 75 and the capacitance component of PDP 1 become a resonant state, the charge on the capacitance component of PDP 1 is restored by the capacitor 75.
The clamping circuit 80 is configured with switches S5, S6 and diodes 81, 82. In the clamping circuit 80, the switches S5, S6 are controlled as to on/off state by the control circuit 22, to set the scan electrode 2 of PDP 1 at a voltage Vs or a ground level. The clamping circuit 90 is configured with switches S7, S8 and diodes 91, 92. In the clamping circuit 90, the switches S7, S8 are controlled as to on/off state by the control circuit 22, to set the scan electrode 2 of PDP 1 at a voltage Vs or a ground level.
FIG. 6 is a figure explaining the principle of gradation display method according to the Address Display Separate method for use on the PDP of FIG. 2, wherein time is taken on the abscissa while in-PDP scan electrode number (1, . . . , n) is taken on the ordinate.
In the PDP, one field TF is segmented into six sub-fields 1SF, 2SF, . . . , 6SF weighted based on the intensity level, as shown in FIG. 6. Each sub-field is segmented into an initializing time period (referred also to as “preparatory discharge time period”) T1, a scanning time period T2 and a sustaining time period T3. The slant line within each scanning time period T2 represents the timing of a scan pulse to be applied line-sequentially to the scan electrode 2. In case the scan pulse and the data pulse, to be applied to the data electrode 4, are both applied simultaneously, a write discharge takes place. The sustaining time period T3 is a time period for which the unit cell 5 is caused for display-emission.
In the sustaining time period T3, sustain pulses are applied alternately to the scan electrode 2 and the sustain electrode 3. In the cell in which a discharge occurs in the scanning time period T2, emission takes place at an intensity commensurate with the length of the sustaining time period T3 (i.e. the number of sustain pulses). In FIG. 6, the sub-fields 1SF, 2SF, . . . , 6SF have respectively sustaining time periods T3 set in length ratio of 1:2:4:8:16:32 and therefore by combining the respective emissions in the sustaining time periods T3, on-screen display is performed with 64 levels (0-63) of intensities. For example, where to make on-screen display at 29-th intensity level, control is made to cause an emission in sub-field 1SF (level: 1), sub-field 3SF (level: 4), sub-field 4SF (level: 8) and sub-field 5SF (level: 16) in a period of one field TF.
FIG. 7 is a figure showing an essential part of a drive waveform for use in the Address Display Separate method.
Referring to the figure, explanation is made on the drive method according to the Address Display Separate method.
The sustain electrode 3 is applied with a voltage shown as a waveform Sus, as shown in FIG. 7, while the scan electrode 2 is sequentially applied with a voltage shown as wavefors Scan1−Scann. Meanwhile, the data electrode 4 is applied with a voltage shown as a waveform Data. In the initializing time period T1, a sustain erase waveform-b is applied to the scan electrode 2. Initialization (reset) is made as to the difference in formation amount of wall charge that is a charge built up, by discharge, on a dielectric layer (transparent dielectric layer 14 and white dielectric layer 16) over each electrode within the unit cell 5 due to the presence/absence of a sustain discharge in the preceding sub-field. Meanwhile, in the initializing time period T1, a priming effect occurs which is for facilitating a discharge in line-sequentially writing data depending upon display data in the scanning time period T2 subsequent to the initializing time period T1, and further the wall charge is made in a state optimal for write discharge. In this case, a priming waveform-c and priming erase waveform-d are applied to the scan electrode 2. By the priming waveform-c, a weak discharge takes place regardless of occurrence/non-occurrence of a sustain discharge in the preceding sub-field. The occurrence of a priming particle within the discharge space 19 results in a status a write discharge is ready to occur.
In the scanning time period T2, video information is written to the unit cells 5 by changing the status of wall charge depending upon the presence/absence of a write discharge occurrence, sequentially on a scan-electrode 2 basis and correspondingly to a video signal “in”. Namely, in the scanning time period T2, a scan pulse-a is sequentially applied to Scan1, Scan2, . . . , Scann of the scan electrodes 2 being applied with a scanning-base voltage Vbw. In accordance with the scan pulse-a, a data pulse-e is applied to D1, D2, . . . , Dm of the data electrodes 4 according to a display pattern. Incidentally, the slant line on the data pulse in FIG. 7 represents that a data pulse-e is applied or not applied according to the video signal. In the on-cell, a data pulse-e is applied during the application of a scan pulse-a, to cause a write discharge. Meanwhile, in the off-cell, a data pulse-e is not applied not to cause a write discharge. After applying the scan pulse-a to all the scan electrodes 2, transition is into a sustaining time period T3.
In the sustaining time period T3, a sustain pulse f at voltage Vs is applied alternately to all the scan electrodes 2 and all the sustain electrodes 3. In the on-cell where a write discharge occurred, a sustain discharge is caused by the wall charge formed upon the write discharge. Once a sustain discharge takes place, the wall charge is inverted in polarity to invert the polarity of the sustain pulse-f, thereby causing a sustain discharge again. Each time the sustain pulse inverts in polarity, a sustain discharge is caused to make on-status.
FIG. 8 is a waveform diagram explaining the operations of various points in FIG. 7 in the sustaining time period T3 where the FIG. 1 charge recovering circuit 14 is in a configuration shown in FIG. 4.
In (a) and (b) of FIG. 8, there is shown a magnified drive waveform in the sustaining time period T3 while, in (c) of FIG. 8, there is shown a visible-light emission waveform of a sustain discharge.
Namely, a sustain pulse-f has a charge-recovering time period T31, a clamp timing period T32, a charge-recovering time period T33, and a clamp timing period T34. In the charge-recovering time period T31, the switch S1 of the resonant circuit 30 is on in state so that voltages mutually reverse in phase are applied from the resonant circuit 30 to the scan electrode 2 and the sustain electrode 3. In the clamp timing period T32, the switch S3 of the clamping circuit 40 is on in state so that a voltage Vs is applied from the clamping circuit 40 to the scan electrode 2. Furthermore, the switch S6 of the clamping circuit 50 is on in state so that the sustain electrode 3 is at a ground level. In the charge-recovering time period T33, the switch S2 of the resonant circuit 30 is on in state so that mutually-reverse voltages are applied from the resonant circuit 30 to the scan electrode 2 and the sustain electrode 3. In the clamp timing period T34, the switch S4 of the clamping circuit 40 is on in state so that the scan electrode 2 is at a ground level. Furthermore, the switch S5 of the clamping circuit 50 is on in state so that a voltage Vs is applied from the clamping circuit 50 to the sustain electrode 3.
The start timing t31, t32 in entering the clamp timing period T32, T43 is referred to as clamp start timing while the time of the charge-recovering time period T31, T33 is referred to as a recovering time. In the charge-recovering time period T31, T33, the resonance of the resonant circuit 30 and the cell 5 capacitance component of PDP 1 causes the charge built up on the capacitance component to flow to the scan electrode 2 and sustain electrode 3 thereby causing voltage application. Hence, those are not fixed at particular potentials. Accordingly, as shown in (a) and (b) of FIG. 8, once a sustain discharge begins, the charge flowed to the scan electrode 2 and sustain electrode 3 decreases to decrease the application voltage. Due to this, the sustain discharge once changes toward weakening. However, when voltage is applied from the clamping circuit 40, 50 to the scan electrode 2 and sustain electrode 3 in the clamp start timing t31, t32, the application voltage increases at once and hence change is toward intensification again. For this reason, there is a change in the emission waveform around the clamp start timing t31, t32.
FIG. 9 is a waveform diagram explaining the operations at various points in FIG. 7 in the sustaining time period T3 wherein the FIG. 1 charge recovering circuit 14 is in a configuration shown in FIG. 5.
In (a) and (b) of FIG. 9, there is shown a magnified drive waveform in the sustaining time period T3 while, in (c) of FIG. 9, there is shown a visible-light emission waveform of a sustain discharge.
Namely, the sustain pulse-f on the scan electrode 2 has a clamp timing period T41, a charge-recovering time period T42, a clamp timing period T43, A charge-recovering time period T44 and a clamp timing period T45. The sustain pulse-f on the sustain electrode 3 has a charge-recovering time period T51, a clamp timing period T52, a charge-recovering time period T53 and a clamp timing period T54.
The switch S1 of the resonant circuit 60 is on in state in the charge-recovering time period T42 and clamp timing period T43. The switch S2 of the resonant circuit 60 is on in state in the charge-recovering time period T44 and clamp timing period T45. The switch S3 of the resonant circuit 70 is on in-state in the clamp timing period T41, charge-recovering time period T42 and clamp timing period T43. The switch S4 of the resonant circuit 70 is on in state in the charge-recovering time period T53 and clamp timing period T54. The switch S5 of the clamping circuit 80 is on in state in the clamp timing period T43. The switch S6 of the clamping circuit 80 is on in state in the clamp timing period T45. The switch S7 of the clamp circuit 90 is on in state in the clamp timing period T54. The switch S8 of the clamp circuit 90 is on in state in the clamp timing period T52.
For this reason, there encounters a deviation in rise/fall timing in voltages to be applied respectively to the scan electrode 2 and the scan electrode 3, as shown in (a) and (b) in FIG. 9. However, a sustain discharge occurs in the course of the charge-recovering time period T42. The sustain discharge continues straddling the clamp start timing t41. The discharge is once weakened immediately before the clamp start timing t41 and again intensified immediately after the clamp start timing t41. Thus, the emission waveform is nearly similar to that of (c) in FIG. 8, as shown in (c) in FIG. 9.
Besides the plasma display in the above, the art of this kind conventionally includes those of description in the following document, for example.
JP-A-2000-172223 (Abstract, FIG. 1) describes a drive method for a plasma display panel. By allowing a variation between the time from beginning of a charge restoration to fixing to a sustain potential with respect to the sustain pulse and the time from beginning of charge restoration to fixing to a ground potential, a predetermined brightness is obtained when the load of display is great. When the load of display is low, brightness saturation does not occur.
However, the foregoing plasma display involves the following problem.
Namely, in the unit cell 5 of the PDP 1, there is a variation in the discharge initiating threshold voltage, as a minimal application voltage for causing a discharge on the surface-discharge electrode 6, due to the variation in length of the discharge gap 13 and in thickness of the transparent dielectric layer 14 and white dielectric layer 16. Meanwhile, there is a possibility that discharge initiating threshold voltage temporarily differs between the cells having, in nature, the same discharge initiating threshold voltage characteristic, depending upon the immediately preceding state of display (on or off). In case the discharge initiating threshold voltage is different between the unit cells, the emission waveform shown in (c) of FIG. 8 or (c) of FIG. 2 is made different on a unit-cell-5 basis. This makes different on-screen brightness between the unit cells 5, resulting in a problem of a deterioration in the quality of display screen.
Meanwhile, the drive method for a plasma display, described in JP-A-2000-172223, aims at improving the problem that required brightness is not obtainable when the load of display is great while brightness saturation occurs when the load of display is small. This is different in gist from the present invention.